The present application relates generally to an improved data processing apparatus and method and more specifically to mechanisms for resolving coupling timing and slew violations for buffer-dominated designs.
Modern day electronics include components that use integrated circuits. Integrated circuits are electronic circuits formed using Silicon as a substrate and by adding impurities to form solid-state electronic devices, such as transistors, diodes, and resistors. Commonly known as a “chip”, an integrated circuit (IC) is generally encased in hard plastic. The components in modern day electronics generally appear to be rectangular black plastic pellets with connector pins protruding from the plastic encasement.
Circuit designers use a variety of software tools to design electronic circuits that accomplish an intended task. For example, a digital circuit may be designed to accept digital inputs, perform some computation, and produce a digital output. An analog circuit may be designed to accept analog signals, manipulate the analog signals, such as by amplifying, filtering, or mixing the signals, and produce an analog or digital output. Generally, any type of circuit can be designed as an IC.
The software tools used for designing ICs produce, manipulate, or otherwise work with the circuit layout at very small scales. Some of the components that such a tool may manipulate may only measure tens of nanometers across when formed in Silicon. The designs produced and manipulated using these software tools are complex, often including millions of such components interconnected to form an intended electronic circuitry.
Interconnect performance is becoming increasingly dominant over transistor and logic performance in the deep submicron regime. Buffer insertion is a fundamental technology used in modern integrated circuit design methodologies. As gate delays decrease with increasing chip dimensions, however, the number of buffers required quickly rises. That is, traditional methods to resolve timing problems is assuming the design is in a good stage of late mode timing and congestion and then starting to aggressively insert buffers into a current netlist to make the interconnect wire shorter and reduce the coupling capacitance impact. Coupling capacitance is the impact one wire has on another wire. The main drawback of this method is to add extra buffer resources and often make the late mode timing worse by putting buffers in non-optimal distance.
Thus, in addition to timing issues, managing the density of an integrated circuit design is becoming more problematic. The performance of a design highly depends on how packed the logic is geographically in the physical integrated circuit. If the logic is completely spread out, the design is routable but the performance suffers significantly. On the other hand, if the logic is packed, the design is not routable but would yield the best timing characteristics. A packed design is unsuitable for later design changes, such as the insertion of additional logic, or change the size of existing logics, since there is little room for the new logic or the increased size change.